The present invention is related to integrated circuit designs. More particularly, the present invention is directed to a method and system for improving signal integrity in integrated circuit designs.
Signal integrity (SI) represents issues relating to the sources of noise in an integrated circuit (IC) design and their effect on performance. It has become increasingly important in recent years because advancements in IC design have led to a rise in noise level as well as a decline in immunity to the noise. For example, smaller process technologies result in greater interconnect densities, which in turn causes capacitive coupling, a growing source of noise. Additionally, designs with higher clock speeds and lower threshold voltages have an increased sensitivity to noise. Noise can affect a signal by destroying the logical information within, which could lead to functional failure, or by changing the timing of a transition, which could cause timing problems.
Traditionally, the design process for an IC begins with a set of design requirements, e.g., size, speed, purpose, etc. From these requirements, components (also known as cells or blocks) are created from scratch and/or selected from libraries of existing components. These components are then placed in such a way as to minimize the size of the chip. Routing then connects various terminals (also known as ports) of these cells in a manner that would satisfy the design requirements. The connection between ports with the same ID is called a net.
Previously, SI effects were either ignored altogether or analyzed and repaired after routing was complete. However, because the number of potential violations and their likelihood of seriously impacting the design have increased dramatically, the post-routing approach no longer works well by itself. In addition, pre-routing SI analysis is limited due to difficulties in predicting the timing variations that capacitive coupling between wires could introduce. Moreover, handling signal integrity issues exclusive of other concerns, such as timing and manufacturability, is simply not viable for today's designs as a fix for one problem will likely exacerbate another problem. Accordingly, there is a need for a method and system that can address these issues concurrently.
Embodiments of the present invention provide methods, systems, and mediums for improving signal integrity in integrated circuit designs. In one embodiment, a global routing plan is generated for an integrated circuit design. Signal integrity optimization is then conducted in conjunction with detailed routing based upon the global routing plan.
Further details of aspects, objects, and advantages of the invention are described below in the detailed description, drawings, and claims. Both the foregoing general description and the following detailed description are exemplary and explanatory, and are not intended to be limiting as to the scope of the invention.